[MIRVRegNamer] Avoid opcode hash collision
authorJohn Brawn <john.brawn@arm.com>
Fri, 28 Oct 2022 13:17:01 +0000 (14:17 +0100)
committerJohn Brawn <john.brawn@arm.com>
Wed, 2 Nov 2022 13:53:12 +0000 (13:53 +0000)
commit2d8c1597e51c39d8db1c9428d65e6ef6d6a1d5c1
tree344292e459cd12e7e812135c14cf047d9702482d
parent88ac25b357aa2ac96fd1e44cd9fd12d2f1dd189a
[MIRVRegNamer] Avoid opcode hash collision

D121929 happens to cause CodeGen/MIR/AArch64/mirnamer.mir to fail due
to a hash collision caused by adding two extra opcodes. The collision
is only in the top 19 bits of the hashed opcode so fix this by just
using the whole hash (in fixed width hex for consistency) instead of
the top 5 decimal digits.

Differential Revision: https://reviews.llvm.org/D137155
llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
llvm/test/CodeGen/MIR/AArch64/mir-canon-constant-pool-hash.mir
llvm/test/CodeGen/MIR/AArch64/mir-canon-jump-table.mir
llvm/test/CodeGen/MIR/AArch64/mirCanonCopyCopyProp.mir
llvm/test/CodeGen/MIR/AArch64/mirCanonIdempotent.mir
llvm/test/CodeGen/MIR/AArch64/mirnamer.mir
llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
llvm/test/CodeGen/MIR/X86/mir-canon-hash-bb.mir
llvm/test/CodeGen/MIR/X86/mircanon-flags.mir