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(parent: 5491385) | patch
i965/vec4/nir: allocate two registers for dvec3/dvec4
authorConnor Abbott <connor.w.abbott@intel.com>
Mon, 29 Feb 2016 11:35:05 +0000 (12:35 +0100)
committerSamuel Iglesias Gonsálvez <siglesias@igalia.com>
Tue, 3 Jan 2017 10:26:50 +0000 (11:26 +0100)
commit2d81a292036445c440e56d07ce3d5294e0411d71
tree523b0942ccb9869fbac37bbc5d405d21d4078c33tree | snapshot
parent54913850aa379f57fcbf7a2dec5ea236cf997646commit | diff
i965/vec4/nir: allocate two registers for dvec3/dvec4

v2 (Curro):
  - Do not special-case for a bit-size of 64, divide the bit_size by 32
    instead.
  - Use DIV_ROUND_UP so we can handle sub-32-bit types.

v3 (Ian):
  - Make num_regs const.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp diff | blob | history
Domain: Graphics System / GL;