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(parent: a4ca2b2) | patch
clk: tegra: Read correct IDDQ register in PLL_SS registration
authorBill Huang <bilhuang@nvidia.com>
Thu, 18 Jun 2015 21:28:39 +0000 (17:28 -0400)
committerThierry Reding <treding@nvidia.com>
Thu, 17 Dec 2015 12:37:58 +0000 (13:37 +0100)
commit2d7f61f37731f635af47615a8a331ffe7f884934
tree57424c3745bc493aca9837f77d97ec8335bbea7ftree | snapshot
parenta4ca2b2fe7252032022d14b4efd462161c91165bcommit | diff
clk: tegra: Read correct IDDQ register in PLL_SS registration

This fixes a bug in tegra_clk_register_pllss() which mistakenly assume
the IDDQ register is the PLL base address.

Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Benson Leung <bleung@chromium.org>
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-pll.c diff | blob | history
Domain: System / Kernel;