drm/i915/pvc: Update forcewake domain for CCS register ranges
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 14 Oct 2022 23:30:04 +0000 (16:30 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Tue, 18 Oct 2022 21:44:50 +0000 (14:44 -0700)
commit2d3093fd5ea0e79cc6ca0e80ca56280ea7b4d0bf
treea4137ec9cadba05d6eed8e8ba7f2b0aae87abcf1
parent21f213e67ecb7488c0fda145d7956e09ecdd43a9
drm/i915/pvc: Update forcewake domain for CCS register ranges

The bspec was just updated with a correction to the forcewake domain
required when accessing registers in the CCS engine ranges (0x1a000 -
0x1ffff and 0x26000 - 0x27fff) on PVC; these ranges require a wake on
the RENDER domain, not the GT domain.

Bspec: 67609
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Harish Chegondi <harish.chegondi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014233004.1053678-1-matthew.d.roper@intel.com
drivers/gpu/drm/i915/intel_uncore.c