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GBE: Enable register spilling for SIMD16.
authorZhigang Gong <zhigang.gong@gmail.com>
Wed, 9 Apr 2014 16:05:26 +0000 (00:05 +0800)
committerZhigang Gong <zhigang.gong@intel.com>
Wed, 16 Apr 2014 01:46:00 +0000 (09:46 +0800)
commit2ce0abf639dda9fc10965ef95ea93e2ad1e87c7c
tree81764251bf4ec5f94d6e5dee09358f5235e468c5tree | snapshot
parentadd15cb38aa2ae0dc8576cb653c8d05584087c5dcommit | diff
GBE: Enable register spilling for SIMD16.

Enable register spilling for SIMD16 mode. Introduce an
new environment variable OCL_SIMD16_SPILL_THRESHOLD to
control the threshold of simd 16 register spilling. Default
value is 16, means when the spilled registers are more than
16, beignet will fallback to simd8.

Signed-off-by: Zhigang Gong <zhigang.gong@gmail.com>
Reviewed-by: "Song, Ruiling" <ruiling.song@intel.com>
backend/src/backend/gen_insn_selection.cpp diff | blob | history
backend/src/backend/gen_reg_allocation.cpp diff | blob | history
Domain: SCM / Uncategorized;