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(parent: d9e0bbd) | patch
AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 30 May 2020 23:50:55 +0000 (19:50 -0400)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Mon, 15 Jun 2020 15:33:16 +0000 (11:33 -0400)
commit2ca552322c29b61e8c20a0b31cf452de88d8af1c
tree68b9850b326eaa0af4f2aea7464a7fca12d01083tree | snapshot
parentd9e0bbd17b0e61e9f59e6f80c748f7893f7e8d9ccommit | diff
AMDGPU/GlobalISel: Fix 8-byte aligned, 96-bit scalar loads

These are legal since we can do a 96-bit load on some subtargets, but
this is only for vector loads. If we can't widen the load, it needs to
be broken down once known scalar. For 16-byte alignment, widen to a
128-bit load.
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h diff | blob | history
llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll [new file with mode: 0644] blob
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir diff | blob | history
Domain: System / Toolchain;