drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 to HW whitelist
authorArun Siluvery <arun.siluvery@linux.intel.com>
Thu, 21 Jan 2016 21:43:50 +0000 (21:43 +0000)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 25 Jan 2016 15:48:28 +0000 (16:48 +0100)
commit2c8580e4e21c17011e78e7ac4e1fbab8b0d632bf
tree45bdc13d115b60f7597d4010e1978175418ccc91
parent3669ab6191b24ee800a5f78d3748b7d96df12115
drm/i915/bxt: Add GEN9_CS_DEBUG_MODE1 to HW whitelist

Required for,
WaDisableObjectLevelPreemptionForTrifanOrPolygon:bxt
WaDisableObjectLevelPreemptionForInstancedDraw:bxt
WaDisableObjectLevelPreemtionForInstanceId:bxt

According to WA database these are only applicable for BXT:A0 but since
A0 and A1 shares the same GT these are extended for A1 as well.

These are also required for SKL until B0 but not adding them because they
are pre-production steppings.

This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.

v2: use lower case in register defines (Nick)
v3: explain purpose of changes (Chris)

Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-5-git-send-email-arun.siluvery@linux.intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_ringbuffer.c