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RegisterCoalescer: Defer clearing implicit_def lanes
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 8 Jan 2019 23:10:47 +0000 (23:10 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 8 Jan 2019 23:10:47 +0000 (23:10 +0000)
commit2c807410fd37942b5b866eecfc52d7f0126db99f
tree786dd2261e6cdf506682e6deb818fb537ef9e4f0tree | snapshot
parent0e3299dc60f038ab6b7224206adb27aa0582865dcommit | diff
RegisterCoalescer: Defer clearing implicit_def lanes

We can't go back and recover the lanes if it turns
out the implicit_def really can't be erased.

Assume all lanes are valid if an unresolved conflict
is encountered. There aren't any tests where this
seems to matter either way, but this seems like a
safer option.

Fixes bug 39602

llvm-svn: 350676
llvm/lib/CodeGen/RegisterCoalescer.cpp diff | blob | history
llvm/test/CodeGen/AMDGPU/regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir [new file with mode: 0644] blob
Domain: System / Toolchain;