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[RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.
authorCraig Topper <craig.topper@sifive.com>
Thu, 6 Apr 2023 02:28:05 +0000 (19:28 -0700)
committerCraig Topper <craig.topper@sifive.com>
Thu, 6 Apr 2023 02:28:05 +0000 (19:28 -0700)
commit2c57868e2e877f73c339796c3374ae660bb77f0d
treea4f8af74589125626cb5c540532de495008d15f4tree | snapshot
parent6dbb2a717a14327e086d22265440dfc9b1d842b6commit | diff
[RISCV] Add vector load/store intrinsics to getTgtMemIntrinsic.

This constructs a proper memory operand for these intrinsics.

Segment load/store will be added in a separate patch.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D147119
llvm/lib/Target/RISCV/RISCVISelLowering.cpp diff | blob | history
llvm/test/CodeGen/RISCV/early-clobber-tied-def-subreg-liveness.ll diff | blob | history
llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll diff | blob | history
Domain: System / Toolchain;