RISC-V: Fix [dis]assembly of srai/srli
authorAndrew Waterman <andrew@sifive.com>
Mon, 13 Mar 2017 19:46:33 +0000 (12:46 -0700)
committerPalmer Dabbelt <palmer@dabbelt.com>
Tue, 14 Mar 2017 16:23:18 +0000 (09:23 -0700)
commit2c232b8361a044d689d12161b7a645d238586f5e
tree13d9921279be84a076b200f61f5b606d113ef0dc
parent9216a6f33592c350ad50696d5571c82e47b71a5e
RISC-V: Fix [dis]assembly of srai/srli

These were simple copy/paste errors from the compressed left shift
pattern, which can't have a 0-register.
opcodes/ChangeLog
opcodes/riscv-opc.c