[AArch64][SVE] Asm: add aliases for unpredicated bitwise logical instructions
authorCullen Rhodes <cullen.rhodes@arm.com>
Mon, 29 Apr 2019 15:27:27 +0000 (15:27 +0000)
committerCullen Rhodes <cullen.rhodes@arm.com>
Mon, 29 Apr 2019 15:27:27 +0000 (15:27 +0000)
commit2c0d5043a753754949926019f8de92984ec9c181
tree37a0c023072fd910484efe419a726ccc1000f8cb
parent0d339460f1b9d50bece25f3217d912c731eb17bd
[AArch64][SVE] Asm: add aliases for unpredicated bitwise logical instructions

This patch adds aliases for element sizes .B/.H/.S to the
AND/ORR/EOR/BIC bitwise logical instructions. The assembler now accepts
these instructions with all element sizes up to 64-bit (.D). The
preferred disassembly is .D.

llvm-svn: 359457
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/MC/AArch64/SVE/and.s
llvm/test/MC/AArch64/SVE/bic.s
llvm/test/MC/AArch64/SVE/eor.s
llvm/test/MC/AArch64/SVE/orr.s