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(parent: 4fb873c) | patch
gpu: ipu-v3: Fix i.MX51 CSI control registers offset
authorAlexander Shiyan <shc_work@mail.ru>
Thu, 20 Dec 2018 08:06:38 +0000 (11:06 +0300)
committerPhilipp Zabel <p.zabel@pengutronix.de>
Thu, 17 Jan 2019 13:58:55 +0000 (14:58 +0100)
commit2c0408dd0d8906b26fe8023889af7adf5e68b2c2
tree6dfd05bb395da7b3ac66bba0c479a1a2b686e6bdtree | snapshot
parent4fb873c9648e383206e0a91cef9b03aa54066acacommit | diff
gpu: ipu-v3: Fix i.MX51 CSI control registers offset

The CSI0/CSI1 registers offset is at +0xe030000/+0xe038000 relative
to the control module registers on IPUv3EX.
This patch fixes wrong values for i.MX51 CSI0/CSI1.

Fixes: 2ffd48f2e7 ("gpu: ipu-v3: Add Camera Sensor Interface unit")

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
drivers/gpu/ipu-v3/ipu-common.c diff | blob | history
Domain: System / Kernel;