Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register...
authorDaniel Sanders <daniel_l_sanders@apple.com>
Thu, 1 Aug 2019 23:27:28 +0000 (23:27 +0000)
committerDaniel Sanders <daniel_l_sanders@apple.com>
Thu, 1 Aug 2019 23:27:28 +0000 (23:27 +0000)
commit2bea69bf6503ffc9f3cde9a52b5dac1a25e94e1c
tree91dc8f6a4635d24a9c93d1e5080a67b8baae69f8
parent9debb024d44db54b9453459d3bd98d28c20a163f
Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

llvm-svn: 367633
195 files changed:
llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
llvm/include/llvm/CodeGen/LiveRegUnits.h
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
llvm/include/llvm/CodeGen/MachineRegisterInfo.h
llvm/include/llvm/CodeGen/RegisterClassInfo.h
llvm/include/llvm/CodeGen/RegisterPressure.h
llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h
llvm/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/include/llvm/CodeGen/VirtRegMap.h
llvm/lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
llvm/lib/CodeGen/AsmPrinter/DwarfExpression.cpp
llvm/lib/CodeGen/BranchFolding.cpp
llvm/lib/CodeGen/CalcSpillWeights.cpp
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
llvm/lib/CodeGen/DetectDeadLanes.cpp
llvm/lib/CodeGen/EarlyIfConversion.cpp
llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
llvm/lib/CodeGen/GlobalISel/Utils.cpp
llvm/lib/CodeGen/InlineSpiller.cpp
llvm/lib/CodeGen/LiveDebugValues.cpp
llvm/lib/CodeGen/LiveDebugVariables.cpp
llvm/lib/CodeGen/LiveInterval.cpp
llvm/lib/CodeGen/LiveIntervals.cpp
llvm/lib/CodeGen/LivePhysRegs.cpp
llvm/lib/CodeGen/LiveRangeCalc.cpp
llvm/lib/CodeGen/LiveRangeEdit.cpp
llvm/lib/CodeGen/LiveRangeShrink.cpp
llvm/lib/CodeGen/LiveRegUnits.cpp
llvm/lib/CodeGen/LiveStacks.cpp
llvm/lib/CodeGen/LiveVariables.cpp
llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineCSE.cpp
llvm/lib/CodeGen/MachineCombiner.cpp
llvm/lib/CodeGen/MachineCopyPropagation.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/MachineInstrBundle.cpp
llvm/lib/CodeGen/MachineLICM.cpp
llvm/lib/CodeGen/MachineOperand.cpp
llvm/lib/CodeGen/MachinePipeliner.cpp
llvm/lib/CodeGen/MachineRegisterInfo.cpp
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/MachineTraceMetrics.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/CodeGen/OptimizePHIs.cpp
llvm/lib/CodeGen/PHIElimination.cpp
llvm/lib/CodeGen/PeepholeOptimizer.cpp
llvm/lib/CodeGen/ProcessImplicitDefs.cpp
llvm/lib/CodeGen/RegAllocBase.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/CodeGen/RegAllocGreedy.cpp
llvm/lib/CodeGen/RegAllocPBQP.cpp
llvm/lib/CodeGen/RegisterCoalescer.cpp
llvm/lib/CodeGen/RegisterPressure.cpp
llvm/lib/CodeGen/RegisterScavenging.cpp
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/lib/CodeGen/ShrinkWrap.cpp
llvm/lib/CodeGen/StackMaps.cpp
llvm/lib/CodeGen/StackSlotColoring.cpp
llvm/lib/CodeGen/TailDuplicator.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/CodeGen/TargetRegisterInfo.cpp
llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
llvm/lib/CodeGen/VirtRegMap.cpp
llvm/lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
llvm/lib/Target/AArch64/AArch64CondBrTuning.cpp
llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp
llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
llvm/lib/Target/AArch64/AArch64PBQPRegAlloc.cpp
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp
llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
llvm/lib/Target/AMDGPU/GCNRegPressure.cpp
llvm/lib/Target/AMDGPU/GCNRegPressure.h
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp
llvm/lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp
llvm/lib/Target/AMDGPU/R600RegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp
llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp
llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.h
llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/lib/Target/ARM/A15SDOptimizer.cpp
llvm/lib/Target/ARM/ARMAsmPrinter.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/lib/Target/ARM/ARMCallLowering.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/lib/Target/ARM/ARMScheduleA9.td
llvm/lib/Target/ARM/MLxExpansionPass.cpp
llvm/lib/Target/ARM/Thumb1InstrInfo.cpp
llvm/lib/Target/ARM/Thumb2InstrInfo.cpp
llvm/lib/Target/ARM/ThumbRegisterInfo.cpp
llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
llvm/lib/Target/BPF/BPFMIPeephole.cpp
llvm/lib/Target/Hexagon/BitTracker.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
llvm/lib/Target/Hexagon/HexagonPeephole.cpp
llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
llvm/lib/Target/Hexagon/RDFCopy.cpp
llvm/lib/Target/Hexagon/RDFGraph.cpp
llvm/lib/Target/Hexagon/RDFLiveness.cpp
llvm/lib/Target/Hexagon/RDFRegisters.cpp
llvm/lib/Target/Hexagon/RDFRegisters.h
llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
llvm/lib/Target/Mips/Mips16InstrInfo.cpp
llvm/lib/Target/Mips/MipsInstructionSelector.cpp
llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
llvm/lib/Target/Mips/MipsRegisterBankInfo.cpp
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
llvm/lib/Target/NVPTX/NVPTXPeephole.cpp
llvm/lib/Target/PowerPC/PPCBranchCoalescing.cpp
llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCMIPeephole.cpp
llvm/lib/Target/PowerPC/PPCReduceCRLogicals.cpp
llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
llvm/lib/Target/PowerPC/PPCVSXCopy.cpp
llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
llvm/lib/Target/PowerPC/PPCVSXSwapRemoval.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
llvm/lib/Target/SystemZ/SystemZRegisterInfo.cpp
llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
llvm/lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp
llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp
llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.h
llvm/lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp
llvm/lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp
llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
llvm/lib/Target/X86/X86CallFrameOptimization.cpp
llvm/lib/Target/X86/X86CmovConversion.cpp
llvm/lib/Target/X86/X86DomainReassignment.cpp
llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InstrInfo.cpp
llvm/lib/Target/X86/X86InstructionSelector.cpp
llvm/lib/Target/X86/X86OptimizeLEAs.cpp
llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp