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author	Zhigang Gong <zhigang.gong@linux.intel.com>
	Wed, 9 Jan 2013 08:05:25 +0000 (16:05 +0800)
committer	Zhigang Gong <zhigang.gong@linux.intel.com>
	Wed, 10 Apr 2013 06:51:31 +0000 (14:51 +0800)
commit	2bcaa57079cd108e5ef3145d32bde6af458e6c01
tree	ed8dc08cb6f0675fc610afdb088717203832c8eb	tree \| snapshot
parent	6e5bb074bb9d5c13d04c6781c4e7ec723ef2bce2	commit \| diff

Implement TYPED_WRITE instruction.

This commit implement TypedWrite instruction, covers the IR layer,
LLVM to GEN and the backend including the code gen.

The write_imagei should work now. As TYPED WRITE message only support
SIMD8, we need to call it twice when the execution size is 16 and we
need more data movements.

Signed-off-by: Zhigang Gong <zhigang.gong@linux.intel.com>
Reviewed-by: Lu Guanqun <guanqun.lu@intel.com>

Domain: SCM / Uncategorized;

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backend/src/backend/gen_context.cpp		diff \| blob \| history
backend/src/backend/gen_context.hpp		diff \| blob \| history
backend/src/backend/gen_encoder.cpp		diff \| blob \| history
backend/src/backend/gen_encoder.hpp		diff \| blob \| history
backend/src/backend/gen_insn_gen7_schedule_info.hxx		diff \| blob \| history
backend/src/backend/gen_insn_selection.cpp		diff \| blob \| history
backend/src/backend/gen_insn_selection.hpp		diff \| blob \| history
backend/src/backend/gen_insn_selection.hxx		diff \| blob \| history
backend/src/ir/instruction.cpp		diff \| blob \| history
backend/src/ir/instruction.hpp		diff \| blob \| history
backend/src/llvm/llvm_gen_backend.cpp		diff \| blob \| history