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(parent: 6fb3b72) | patch
x86: ivybridge: Add early LPC init so that serial works
authorSimon Glass <sjg@chromium.org>
Thu, 13 Nov 2014 05:42:15 +0000 (22:42 -0700)
committerSimon Glass <sjg@chromium.org>
Fri, 21 Nov 2014 06:34:12 +0000 (07:34 +0100)
commit2b6051541b562b72d2cf784376a84552da18318d
treec21b6ae92539eb63628f15b52044dd164471aed7tree | snapshot
parent6fb3b72e8745073465b4a5875b7750cc43cbd1afcommit | diff
x86: ivybridge: Add early LPC init so that serial works

The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.

Signed-off-by: Simon Glass <sjg@chromium.org>
arch/x86/cpu/ivybridge/Makefile diff | blob | history
arch/x86/cpu/ivybridge/cpu.c diff | blob | history
arch/x86/cpu/ivybridge/lpc.c [new file with mode: 0644] blob
arch/x86/dts/link.dts diff | blob | history
arch/x86/include/asm/arch-ivybridge/pch.h [new file with mode: 0644] blob
doc/device-tree-bindings/misc/intel-lpc.txt [new file with mode: 0644] blob
Domain: System / Kernel;