[RISCV] Add basic support for the sifive-7-series short forward branch optimization.
authorCraig Topper <craig.topper@sifive.com>
Mon, 17 Oct 2022 19:40:32 +0000 (12:40 -0700)
committerCraig Topper <craig.topper@sifive.com>
Mon, 17 Oct 2022 20:56:22 +0000 (13:56 -0700)
commit2b32e4f98b4f0e9e6a7c301b627ff75d9af8699e
tree914c2b030c9dedb3fe566341dbdd9d877b882bd3
parent5de73d27bd6b9140978b376b34ef3a7231df9aa9
[RISCV] Add basic support for the sifive-7-series short forward branch optimization.

sifive-7-series has macrofusion support to convert a branch over
a single instruction into a conditional instruction. This can be
an improvement if the branch is hard to predict.

This patch adds support for the most basic case, a branch over a
move instruction. This is implemented as a pseudo instruction so
we can hide the control flow until all code motion passes complete.

I've disabled a recent select optimization if this feature is enabled
in the subtarget.

Related gcc patch for the same optimization https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg211045.html

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D135814
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVSchedRocket.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVSchedule.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll [new file with mode: 0644]