drm/i915: Enable DisplayPort in Valleyview
authorVijay Purushothaman <vijay.a.purushothaman@intel.com>
Thu, 27 Sep 2012 13:43:06 +0000 (19:13 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Fri, 28 Sep 2012 15:02:08 +0000 (17:02 +0200)
commit2a8f64ca23447248efaf87c5c7c2cb0c5c3f27e8
tree6a0050828820fb80994bfbcba81ae388534257ca
parent74a4dd2e4594804ffeb04b3e60ff4cfbf6b8ce10
drm/i915: Enable DisplayPort in Valleyview

In valleyview voltageswing, pre-emphasis and lane control registers can
be programmed only through the h/w side band fabric.

Cleaned up DPLL calculations for Valleyview to support multi display
configurations.

v2: Based on Daniel's feedbacak, moved crt hotplug detect work around as separate
patch. Also moved i9xx_update_pll_dividers to i8xx_update_pll and
i9xx_update_pll.

Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com>
Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: drop spurious whitespace changes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_reg.h
drivers/gpu/drm/i915/intel_display.c