perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support
authorKan Liang <kan.liang@linux.intel.com>
Wed, 30 Jun 2021 21:08:34 +0000 (14:08 -0700)
committerPeter Zijlstra <peterz@infradead.org>
Fri, 2 Jul 2021 13:58:40 +0000 (15:58 +0200)
commit2a8e51eae7c83c29795622cfc794cf83436cc05d
tree6fdae998a0a01441a70afd443c2abc60cd6c7266
parentda5a9156cd2a3be2b00f8defb529ee3e35e5769b
perf/x86/intel/uncore: Add Sapphire Rapids server M3UPI support

M3 Intel UPI is the interface between the mesh and the Intel UPI link
layer. It is responsible for translating between the mesh protocol
packets and the flits that are used for transmitting data across the
Intel UPI interface.

The layout of the control registers for a M3UPI uncore unit is similar
to a UPI uncore unit.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-11-git-send-email-kan.liang@linux.intel.com
arch/x86/events/intel/uncore_snbep.c