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(parent: dd2c028) | patch
drm/amd/display: Avoid setting pixel rate divider to N/A
authorTaimur Hassan <Syed.Hassan@amd.com>
Fri, 11 Nov 2022 19:11:00 +0000 (14:11 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 23 Nov 2022 14:01:53 +0000 (09:01 -0500)
commit2a5dd86a69ea5435f1a837bdb7fafcda609a7c91
tree462c247a584489aa07fa551d7856da66c6beb38ftree | snapshot
parentdd2c028c1395d622df7ddd6837f8ab2dc94008eecommit | diff
drm/amd/display: Avoid setting pixel rate divider to N/A

[Why]
Pixel rate divider values should never be set to N/A (0xF) as the K1/K2
field is only 1/2 bits wide.

[How]
Set valid divider values for virtual and FRL/DP2 cases.

Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Brian Chang <Brian.Chang@amd.com>
Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_dccg.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn314/dcn314_hwseq.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_dccg.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c diff | blob | history
Domain: System / Kernel;