clk: ingenic/jz4740: Fix incorrect dividers for main clocks
authorPaul Cercueil <paul@crapouillou.net>
Thu, 2 May 2019 21:24:59 +0000 (23:24 +0200)
committerStephen Boyd <sboyd@kernel.org>
Fri, 7 Jun 2019 18:48:59 +0000 (11:48 -0700)
commit2a1a703635a01a98d36cd5c8079dd49c1e006cf6
treeb80101e03a776bc355e641da3b654935ae72e4cd
parenta9fa2893fcc64bd32cbc46bfb7aa09bde8175987
clk: ingenic/jz4740: Fix incorrect dividers for main clocks

The main clocks (cclk, hclk, pclk, mclk, lcd) were using
incorrect dividers, and thus reported an incorrect rate.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/jz4740-cgu.c