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[SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are...
authorCraig Topper <craig.topper@gmail.com>
Tue, 31 Mar 2020 05:01:37 +0000 (22:01 -0700)
committerCraig Topper <craig.topper@gmail.com>
Tue, 31 Mar 2020 06:21:58 +0000 (23:21 -0700)
commit2a07221cf3029f2b55503e1c3847699eb6090ad6
tree7893e16bbef18f6129cc305c8d56eadd5df53580tree | snapshot
parent339b34266c1b54a9b5ff2f83cfb1da9cd8c9d90acommit | diff
[SelectionDAG] Add an assert that the input VT and output VT for ISD::FREEZE are the same.

Differential Revision: https://reviews.llvm.org/D77092
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
Domain: System / Toolchain;