MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum
authorTokunori Ikegami <ikegami@allied-telesis.co.jp>
Sun, 3 Jun 2018 14:02:01 +0000 (23:02 +0900)
committerJames Hogan <jhogan@kernel.org>
Mon, 18 Jun 2018 21:19:50 +0000 (22:19 +0100)
commit2a027b47dba6b77ab8c8e47b589ae9bbc5ac6175
treec57c89e3287c4d936fd424a97e28f09f8737fe9e
parent326345f995a83e326fa2e01d54bfa9a6a307bd4d
MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum

The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as
below.

  R10: PCIe Transactions Periodically Fail

    Description: The BCM5300X PCIe does not maintain transaction ordering.
                 This may cause PCIe transaction failure.
    Fix Comment: Add a dummy PCIe configuration read after a PCIe
                 configuration write to ensure PCIe configuration access
                 ordering. Set ES bit of CP0 configu7 register to enable
                 sync function so that the sync instruction is functional.
    Resolution:  hndpci.c: extpci_write_config()
                 hndmips.c: si_mips_init()
                 mipsinc.h CONF7_ES

This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX.
Also the dummy PCIe configuration read is already implemented in the
Linux BCMA driver.

Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y
too so that the sync instruction is externalised.

Signed-off-by: Tokunori Ikegami <ikegami@allied-telesis.co.jp>
Reviewed-by: Paul Burton <paul.burton@mips.com>
Acked-by: Hauke Mehrtens <hauke@hauke-m.de>
Cc: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: Rafał Miłecki <zajec5@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: stable@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/19461/
Signed-off-by: James Hogan <jhogan@kernel.org>
arch/mips/bcm47xx/setup.c
arch/mips/include/asm/mipsregs.h