clk: samsung: exynos4: Propagate rate change of SPI dividers
authorTomasz Figa <t.figa@samsung.com>
Wed, 4 Dec 2013 13:09:46 +0000 (14:09 +0100)
committerMarek Szyprowski <m.szyprowski@samsung.com>
Thu, 15 May 2014 05:25:43 +0000 (07:25 +0200)
commit29fa37b2f8f95aa19e2fd662b7ddfda6011a22f4
treed2afada2d8679d70cf0c92e2169b378662f79d40
parentd37a08958ce87617704c438aa2560939fd0cc437
clk: samsung: exynos4: Propagate rate change of SPI dividers

This patch adds missing CLK_SET_RATE_PARENT flag to div_spi{0,1,2} clocks
to allow rate change propagation to div_spi{0,1,2}_pre. This fixes the
problem with SPI bus clock rate setting.

Change-Id: I26ef7028297914d5c99e55f0e9fa6dc6a9292e94
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
drivers/clk/samsung/clk-exynos4.c