clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers
authorDouglas Anderson <dianders@chromium.org>
Fri, 2 Sep 2016 03:26:23 +0000 (20:26 -0700)
committerHeiko Stuebner <heiko@sntech.de>
Sun, 4 Sep 2016 21:45:50 +0000 (23:45 +0200)
commit29edeccb4445123a0457a308d3ff67ddd0e34f97
tree0a1df37fd41d192d6b3ad1fc9542a6bfc127ab90
parentfd75b345bb3d97ee4b2aad1d313e8ffe627ce7e7
clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers

Currently the fractional divider clock time can't handle the
CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers,
there is no clk_divider_bestdiv() function to try speeding up the parent
to see if it helps things.

Eventually someone could try to figure out how to make fractional
dividers able to use CLK_SET_RATE_PARENT, but until they do let's not
confuse the common clock framework (and anyone using it) by setting the
flag.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3399.c