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(parent: cd23492) | patch
drm/radeon: allocate PPLLs from low to high
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 5 Oct 2012 14:22:02 +0000 (10:22 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 15 Oct 2012 17:21:00 +0000 (13:21 -0400)
commit29dbe3bcd2e28e71823febdca989d63d5c27d152
tree167612c387fdc175e2b8aa9d74da30d9a751339etree | snapshot
parentcd23492af3d4401c02c48a4bebe5995c9498eac5commit | diff
drm/radeon: allocate PPLLs from low to high

The order shouldn't matter, but there have been problems
reported on certain older asics.  This behaves more
like the original code before the PPLL allocation
rework.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: Markus Trippelsdorf <markus@trippelsdorf.de>
drivers/gpu/drm/radeon/atombios_crtc.c diff | blob | history
Domain: System / Kernel;