[X86][Costmodel] Load/store i32/f32 Stride=6 VF=8 interleaving costs
authorRoman Lebedev <lebedev.ri@gmail.com>
Tue, 5 Oct 2021 13:28:03 +0000 (16:28 +0300)
committerRoman Lebedev <lebedev.ri@gmail.com>
Tue, 5 Oct 2021 13:58:57 +0000 (16:58 +0300)
commit2996a2b50fe39784b4c98748ba2a5b9595dc40f4
tree7464c5e34cde0591e4293a7d3635dae053375c88
parentd51532d8aad529fcefeedd686f0f1d2d967661f5
[X86][Costmodel] Load/store i32/f32 Stride=6 VF=8 interleaving costs

The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/jK85GWKaK - for intels `Block RThroughput: =31.0`; for ryzens, `Block RThroughput: <=17.0`
So could pick cost of `31`.

For store we have:
https://godbolt.org/z/hPWWhEEf9 - for intels `Block RThroughput: =33.0`; for ryzens, `Block RThroughput: <=13.8`
So we could pick cost of `33`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D111089
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll