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(merge: 246c9f5 9321015)
ASoC: Use maple tree register cache for Everest Semi
authorMark Brown <broonie@kernel.org>
Tue, 20 Jun 2023 14:23:56 +0000 (15:23 +0100)
committerMark Brown <broonie@kernel.org>
Tue, 20 Jun 2023 14:23:56 +0000 (15:23 +0100)
commit29735f6fb0f57c8010c9486216361c0f68c90226
treebc92a9989002250a49c25ed6f65b11bd6eb19058tree | snapshot
parent246c9f586c7c840b88efc874c949706d3f7df30ccommit | diff
parent9321015a5f40891e7cb094c6f68f6d4f67b5f3dccommit | diff
ASoC: Use maple tree register cache for Everest Semi

Merge series from Mark Brown <broonie@kernel.org>:

Several of the Everest Semi CODECs only support single register read and
write operations and therefore do not benefit from using the rbtree
cache over the maple tree cache, convert them to the more modern maple
tree cache.
Domain: System / Kernel;