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ASoC: fsl_micfil: explicitly clear software reset bit
authorShengjiu Wang <shengjiu.wang@nxp.com>
Sat, 7 May 2022 12:14:13 +0000 (20:14 +0800)
committerMark Brown <broonie@kernel.org>
Wed, 11 May 2022 16:42:49 +0000 (17:42 +0100)
commit292709b9cf3ba470af94b62c9bb60284cc581b79
treef5b5865fc87e9658f388a0954143922b436438d8tree | snapshot
parenta962890a5a3cce903ff7c7a19fadee63ed9efdc7commit | diff
ASoC: fsl_micfil: explicitly clear software reset bit

SRES is self-cleared bit, but REG_MICFIL_CTRL1 is defined as
non volatile register, it still remain in regmap cache after set,
then every update of REG_MICFIL_CTRL1, software reset happens.
to avoid this, clear it explicitly.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1651925654-32060-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
sound/soc/fsl/fsl_micfil.c diff | blob | history
Domain: System / Kernel;