drm/i915/dg2: Add MPLLB programming for SNPS PHY
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 23 Jul 2021 17:42:32 +0000 (10:42 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Thu, 29 Jul 2021 16:05:25 +0000 (09:05 -0700)
commit29081008047892acb39099c39d39f84c2e7fb028
treeaade3202ded97a9cdb41443ff8dbd3a0b5ee8e12
parent65ad82b2a3e89bbad6a9337b91dab36798e198dd
drm/i915/dg2: Add MPLLB programming for SNPS PHY

DG2's SNPS PHYs incorporate a dedicated port PLL called MPLLB which
takes the place of the shared DPLLs we've used on past platforms.  Let's
add the MPLLB programming sequences; they'll be plugged into the rest of
the code in future patches.

Bspec: 54032
Bspec: 53881
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Nidhi Gupta <nidhi1.gupta@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210723174239.1551352-24-matthew.d.roper@intel.com
drivers/gpu/drm/i915/Makefile
drivers/gpu/drm/i915/display/intel_display.c
drivers/gpu/drm/i915/display/intel_display_types.h
drivers/gpu/drm/i915/display/intel_dpll.c
drivers/gpu/drm/i915/display/intel_snps_phy.c [new file with mode: 0644]
drivers/gpu/drm/i915/display/intel_snps_phy.h [new file with mode: 0644]
drivers/gpu/drm/i915/i915_reg.h