riscv: setup per-hart stack earlier
authorBo Gan <ganboing@gmail.com>
Sun, 11 Jun 2023 23:54:17 +0000 (16:54 -0700)
committerLeo Yu-Chi Liang <ycliang@andestech.com>
Mon, 24 Jul 2023 05:17:26 +0000 (13:17 +0800)
commit28ff3f16c432f53670d4f3867f003e0a86a5e1e6
treed5b8649cab72a057c2b44e223bbbcd12107ff3e4
parent247aa5a191159ea7e03bf1918e22fbbb784cd410
riscv: setup per-hart stack earlier

Harts need to use per-hart stack before any function call, even if that
function is a simple one. When the callee uses stack for register save/
restore, especially RA, if nested call, concurrent access by multiple
harts on the same stack will cause data-race.

This patch sets up SP before `board_init_f_alloc_reserve`. A side effect
of this is that the memory layout has changed as the following:

+----------------+        +----------------+ <----- SPL_STACK/
|  ......        |        |  hart 0 stack  |        SYS_INIT_SP_ADDR
|  malloc_base   |        +----------------+
+----------------+        |  hart 1 stack  |
|  GD            |        +----------------+ If not SMP, N=1
+----------------+        |  ......        |
|  hart 0 stack  |        +----------------+
+----------------+   ==>  |  hart N-1 stack|
|  hart 1 stack  |        +----------------+
+----------------+        |  ......        |
|  ......        |        |  malloc_base   |
+----------------+        +----------------+
|  hart N-1 stack|        |  GD            |
+----------------+        +----------------+
|                |        |                |

Signed-off-by: Bo Gan <ganboing@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Leo <ycliang@andestech.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
arch/riscv/cpu/start.S