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(parent: c672041) | patch
crypto: marvell/cesa - irq balance
authorSven Auhagen <Sven.Auhagen@voleatech.de>
Tue, 21 Jul 2020 04:40:27 +0000 (06:40 +0200)
committerHerbert Xu <herbert@gondor.apana.org.au>
Fri, 31 Jul 2020 08:09:00 +0000 (18:09 +1000)
commit28ee8b0912ca2ff68c2c03ff97bf1c22634c7942
treef5d20e35e0dbc007af249cb1fc7e6af97fa36d08tree | snapshot
parentc6720415907f21b9c53efbe679b96c3cc9d06404commit | diff
crypto: marvell/cesa - irq balance

Balance the irqs of the marvell cesa driver over all
available cpus.
Currently all interrupts are handled by the first CPU.

From my testing with IPSec AES 256 SHA256
on my clearfog base with 2 Cores I get a 2x speed increase:

Before the patch: 26.74 Kpps
With the patch: 56.11 Kpps

Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
drivers/crypto/marvell/cesa/cesa.c diff | blob | history
drivers/crypto/marvell/cesa/cesa.h diff | blob | history
Domain: System / Kernel;