arm64: errata: Add Cortex-A510 to the repeat tlbi list
authorJames Morse <james.morse@arm.com>
Mon, 4 Jul 2022 15:57:32 +0000 (16:57 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Mon, 5 Sep 2022 08:30:04 +0000 (10:30 +0200)
commit285e77dbb36ff216244367acb8f2d436b941e78a
treefde141f3ba8261cba96ef78070f93fef238ea015
parentda60ddd80d09f8371fbba1a238a4b318d13ba698
arm64: errata: Add Cortex-A510 to the repeat tlbi list

commit 39fdb65f52e9a53d32a6ba719f96669fd300ae78 upstream.

Cortex-A510 is affected by an erratum where in rare circumstances the
CPUs may not handle a race between a break-before-make sequence on one
CPU, and another CPU accessing the same page. This could allow a store
to a page that has been unmapped.

Work around this by adding the affected CPUs to the list that needs
TLB sequences to be done twice.

Signed-off-by: James Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20220704155732.21216-1-james.morse@arm.com
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Lucas Wei <lucaswei@google.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Documentation/arm64/silicon-errata.rst
arch/arm64/Kconfig
arch/arm64/kernel/cpu_errata.c