[X86] Teach shuffle lowering to recognize 128/256 bit insertions into a zero vector.

[X86] Teach shuffle lowering to recognize 128/256 bit insertions into a zero vector.

This regresses a couple cases in the shuffle combining test. But those cases use intrinsics that InstCombine knows how to turn into a generic shuffle earlier. This should give opportunities to fold this earlier in InstCombine or DAG combine.

llvm-svn: 324709