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(parent: 7e856d0) | patch
i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD
authorJordan Justen <jordan.l.justen@intel.com>
Wed, 28 May 2014 16:05:37 +0000 (09:05 -0700)
committerJordan Justen <jordan.l.justen@intel.com>
Sat, 16 Aug 2014 03:11:41 +0000 (20:11 -0700)
commit27f5fa7a3777332b2e60ccf10dc636ad84a3c478
treeb916d200e7d2a53222bbddcee32b4d64720ca694tree | snapshot
parent7e856d0b180d3fc0c25f94156ded4a539f456030commit | diff
i965: Allow forcing miptree->array_layout = ALL_SLICES_AT_EACH_LOD

gen6 does not support multiple miplevels with separate
stencil/hiz. Therefore we need to layout its miptree with no mipmap
spacing between the slices of each miplevel.

v3:
 * Use new array_layout enum

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
src/mesa/drivers/dri/i965/intel_fbo.c diff | blob | history
src/mesa/drivers/dri/i965/intel_mipmap_tree.c diff | blob | history
src/mesa/drivers/dri/i965/intel_mipmap_tree.h diff | blob | history
src/mesa/drivers/dri/i965/intel_tex.c diff | blob | history
src/mesa/drivers/dri/i965/intel_tex_image.c diff | blob | history
src/mesa/drivers/dri/i965/intel_tex_subimage.c diff | blob | history
src/mesa/drivers/dri/i965/intel_tex_validate.c diff | blob | history
Domain: Graphics System / GL;