drm/i915: Make sure we respect n.max on VLV
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 24 Sep 2013 18:26:24 +0000 (21:26 +0300)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 10 Oct 2013 10:46:52 +0000 (12:46 +0200)
commit27e639bf024a0706015dbb348eb32619a9bb9329
tree3600c170f85006fbf5b6f246887fd9f8dd3d6308
parentc1a9ae43885246df7a35c790960d7a703b2841d4
drm/i915: Make sure we respect n.max on VLV

We limit the maximum n divider value in order to make sure the PLL's
reference inout is at least 19.2 MHz. I assume that is done to satisfy
some hardware requirement.

However we never check whether that calculated limit is below the
maximum supoorted N divider value (7). In practice that is always true
since we only support 100 MHz reference clock, but making the code
safe against higher reference clocks seems like a reasoanble thing to
do.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/intel_display.c