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[X86] Correct 256 vpmovzx/vpmovsx isel patterns to check HasAVX2 instead of HasAVX...
authorCraig Topper <craig.topper@intel.com>
Wed, 21 Nov 2018 01:39:38 +0000 (01:39 +0000)
committerCraig Topper <craig.topper@intel.com>
Wed, 21 Nov 2018 01:39:38 +0000 (01:39 +0000)
commit27a5896fe86d6ffe22158b6fff9d15a0cc1719e1
tree676224576551d928196114b2e062fd131719d913tree | snapshot
parent8b48587f5bffd3da398d23e903ad9bd9b16ac3a6commit | diff
[X86] Correct 256 vpmovzx/vpmovsx isel patterns to check HasAVX2 instead of HasAVX to prevent fast-isel from using them incorrectly.

These are AVX2 instructions, but have been incorrectly marked in tablegen for a while. This wasn't a problem until r346784 switched the patterns to use target independent ISD opcodes. This made the patterns visible to fast isel.

Fixes PR39733

llvm-svn: 347375
llvm/lib/Target/X86/X86InstrSSE.td diff | blob | history
llvm/test/CodeGen/X86/pr39733.ll [new file with mode: 0644] blob
Domain: System / Toolchain;