Merge branch 'CR_877_Timer_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'
authorandy.hu <andy.hu@starfivetech.com>
Sun, 24 Apr 2022 13:55:18 +0000 (13:55 +0000)
committerandy.hu <andy.hu@starfivetech.com>
Sun, 24 Apr 2022 13:55:18 +0000 (13:55 +0000)
commit279522d7c9af2e41da929a7b3c54318e44396ef7
tree6d0a01d2fa1e1c9d9834d68cd858e9802db30098
parent57d5f707994ed776dc8a28db39881ddf53ab766b
parent9468d85cf915b704be6c3266f62091eeb0887280
Merge branch 'CR_877_Timer_Xingyu.Wu' into 'jh7110_fpga_dev_5.15'

risv:dts:starfive:Add timer clocktree

See merge request sdk/sft-riscvpi-linux-5.10!26