drm/amd/display: Take FEC Overhead into Timeslot Calculation
authorFangzhi Zuo <Jerry.Zuo@amd.com>
Wed, 1 Mar 2023 02:34:58 +0000 (21:34 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 14 Mar 2023 19:35:39 +0000 (15:35 -0400)
commit2792f98cdb1c8fa43bf4ee5ae00349b823a823b7
tree984900bb26ff006bfb80a16a4ea3050042fa84a8
parentd142d4113fd5c3f7afdb48dff4703ae7edddf53d
drm/amd/display: Take FEC Overhead into Timeslot Calculation

8b/10b encoding needs to add 3% fec overhead into the pbn.
In the Synapcis Cascaded MST hub, the first stage MST branch device
needs the information to determine the timeslot count for the
second stage MST branch device. Missing this overhead will leads to
insufficient timeslot allocation.

Cc: stable@vger.kernel.org
Cc: Mario Limonciello <mario.limonciello@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Fangzhi Zuo <Jerry.Zuo@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.h