projects / platform / upstream / llvm.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 8b24e64) | patch
[InstCombine] Try not to demand low order bits for Add
authorJay Foad <jay.foad@amd.com>
Mon, 18 Jul 2022 18:32:40 +0000 (19:32 +0100)
committerJay Foad <jay.foad@amd.com>
Mon, 22 Aug 2022 19:03:53 +0000 (20:03 +0100)
commit2754ff883d9ebf5452a10a2b739262b481cb3458
treed3a2875300a349b384e170a2a7537df04d51648ctree | snapshot
parent8b24e64014efcef3ab56a98ea262cc0c01a03628commit | diff
[InstCombine] Try not to demand low order bits for Add

Don't demand low order bits from the LHS of an Add if:
- they are not demanded in the result, and
- they are known to be zero in the RHS, so they can't possibly
  overflow and affect higher bit positions

This is intended to avoid a regression from a future patch to change
the order of canonicalization of ADD and AND.

Differential Revision: https://reviews.llvm.org/D130075
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp diff | blob | history
llvm/test/Transforms/InstCombine/add2.ll diff | blob | history
llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll diff | blob | history
llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll diff | blob | history
Domain: System / Toolchain;