[VTA][TSIM] Enable TSIM CI Testing (#4407)
authorLiangfu Chen <liangfu.chen@harman.com>
Fri, 17 Jan 2020 23:23:49 +0000 (07:23 +0800)
committerThierry Moreau <tmoreau@octoml.ai>
Fri, 17 Jan 2020 23:23:49 +0000 (15:23 -0800)
commit2738eddf4ad7aded6760466dff36b15e6503050d
treef8aeea49a12e790115489a48d070e4e80fbc4b6f
parent2f8a01f7071deae4503e9b730304a0e4551c9210
[VTA][TSIM] Enable TSIM CI Testing (#4407)

* Update task_python_vta.sh

* install sbt=1.1.1 with apt-get

* update verilator_opt

* install verilator with major version 4.0

* disable multi-threading for now

* bug fix for correcting uop fetch address in LoadUop module

* bug fix for correcting uop fetch address in LoadUop module

* adjustment to read from dram_offset

* enable USE_THREADS with verilator 4.x

* DEBUG: try avoid core dump with verilator 4.x

* bug fix in LoadUop module

* log mega cycles in tsim

* download cat.png to avoid fetching in each run

* bug fix in LoadUop module

* solve dram_even/sram_even issue

* bug fix

* introduce scalalint in ci

* speedup tsim in ci

* bug fix

* lint scala code before building

* disable multi-threading

* split fsim/tsim script

* update Jenkins settings

* duplicate task_python_vta_fsim.sh as task_python_vta.sh for now

Co-authored-by: Thierry Moreau <tmoreau@octoml.ai>
Makefile
tests/scripts/task_python_vta.sh
tests/scripts/task_python_vta_fsim.sh
tests/scripts/task_python_vta_tsim.sh
vta/hardware/chisel/Makefile
vta/hardware/chisel/src/main/scala/core/LoadUop.scala
vta/hardware/dpi/tsim_device.cc
vta/tutorials/frontend/deploy_vision_on_vta.py