clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568
authorSascha Hauer <s.hauer@pengutronix.de>
Wed, 26 Jan 2022 14:55:46 +0000 (15:55 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 13 Apr 2022 18:59:11 +0000 (20:59 +0200)
commit26f0a9e3d04d755636704560cc36c6e042534284
tree06886f7f0be469fbe896d0e8df06a586d7bb79eb
parentcaffa76ded5ab9776bee0dc1aaf8ab6a00906b96
clk: rockchip: drop CLK_SET_RATE_PARENT from dclk_vop* on rk3568

[ Upstream commit ff3187eabb5ce478d15b6ed62eb286756adefac3 ]

The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or
cpll. gpll and cpll also drive many other clocks, so changing the
dclk_vop[012] clocks could change these other clocks as well. Drop
CLK_SET_RATE_PARENT to fix that. With this change the VOP2 driver can
only adjust the pixel clocks with the divider between the PLL and the
dclk_vop[012] which means the user may have to adjust the PLL clock to a
suitable rate using the assigned-clock-rate device tree property.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20220126145549.617165-25-s.hauer@pengutronix.de
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/clk/rockchip/clk-rk3568.c