clk: uniphier: Add missing USB SS-PHY clocks
authorKunihiko Hayashi <hayashi.kunihiko@socionext.com>
Mon, 20 Feb 2023 05:50:31 +0000 (14:50 +0900)
committerMarek Vasut <marex@denx.de>
Wed, 22 Feb 2023 18:40:11 +0000 (19:40 +0100)
commit26dd38af858d28131302a5a7f1102350e53520a5
tree0034991327bb75a44e8f0090866acfae47de3378
parent1c866de57bfcd2250fba09f5c186a4c3c256e31a
clk: uniphier: Add missing USB SS-PHY clocks

The USB SS-PHY needs its own clock, however, some clocks don't have
clock gates. Define missing clock entries for the PHY as reference
clock.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Marek Vasut <marex@denx.de>
drivers/clk/uniphier/clk-uniphier-sys.c