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upstream: [media] mt9p031: Add support for PLL bypass
authorLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Sun, 9 Feb 2014 20:31:47 +0000 (17:31 -0300)
committerChanho Park <chanho61.park@samsung.com>
Tue, 18 Nov 2014 02:59:12 +0000 (11:59 +0900)
commit26c57f1723fe68a50e5eceeac911c7b7528c1700
tree4e6058e951e6aa84918be4f4e5b9ad0fde5ccf27tree | snapshot
parent6f74e689e4011a5e6289cc8c439057fbe992fbbfcommit | diff
upstream: [media] mt9p031: Add support for PLL bypass

When the input clock frequency is out of bounds for the PLL, bypass the
PLL and just divide the input clock to achieve the requested output
frequency.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
drivers/media/i2c/mt9p031.c diff | blob | history
Domain: System / Kernel;