[PowerPC] Fix spilling of vector registers in PEI of EH aware functions
authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Fri, 7 Feb 2020 20:26:11 +0000 (14:26 -0600)
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Fri, 7 Feb 2020 20:41:52 +0000 (14:41 -0600)
commit26bf877ec5ce07eaaf2ebf19e78f26fa59a8e41a
treee8152d8d8b8971040975ff6f8f10552b407f69af
parent499ad45877b930325b641d18e7b8b71094116e49
[PowerPC] Fix spilling of vector registers in PEI of EH aware functions

On little endian targets prior to Power9, we spill vector registers using a
swapping store (i.e. stdxvd2x saves the vector with the two doublewords in
big endian order regardless of endianness). This is generally not a problem
since we restore them using the corresponding swapping load (lxvd2x). However
if the restore is done by the unwinder, the vector register contains data in
the incorrect order.

This patch fixes that by using Altivec loads/stores for vector saves and
restores in PEI (which keep the order correct) under those specific conditions:
- EH aware function
- Subtarget requires swaps for VSX memops (Little Endian prior to Power9)

Differential revision: https://reviews.llvm.org/D73692
llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/test/CodeGen/PowerPC/CSR-fit.ll
llvm/test/CodeGen/PowerPC/reg-scavenging.ll
llvm/test/CodeGen/PowerPC/vsxD-Form-spills.ll