aarch64: Fix mismatched SVE predicate modes [PR94606]

aarch64: Fix mismatched SVE predicate modes [PR94606]

For this testcase we ended up generating the invalid rtl:

(insn 10 9 11 2 (set (reg:VNx16BI 105)
        (and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
                (reg:VNx16BI 104))
            (reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
     (nil))

Fixed by taking the VNx16BI lowpart.  It's safe to do that here because
the gp (r104) masks out the extra odd-indexed bits.

2020-04-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR target/94606
	* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
	the VNx16BI lowpart of the recursively-generated constant.

gcc/testsuite/
	PR target/94606
	* gcc.dg/vect/pr94606.c: New test.