MIPS: Add support for interAptiv cores
authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Wed, 27 Nov 2013 10:07:53 +0000 (10:07 +0000)
committerRalf Baechle <ralf@linux-mips.org>
Wed, 22 Jan 2014 19:19:01 +0000 (20:19 +0100)
commit26ab96dfa9f98d74ef38efbe830d356547a292c1
tree3789a48dbf291811980cde03016eed2dfcde419a
parent0ce7d58ee0d814622bf7b4700925455dd4960ddd
MIPS: Add support for interAptiv cores

The interAptiv is a power-efficient multi-core microprocessor
for use in system-on-chip (SoC) applications. The interAptiv combines
a multi-threading pipeline with a coherence manager to deliver improved
computational throughput and power efficiency. The interAptiv can
contain one to four MIPS32R3 interAptiv cores, system level
coherence manager with L2 cache, optional coherent I/O port,
and optional floating point unit.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6163/
arch/mips/include/asm/cpu-type.h
arch/mips/include/asm/cpu.h
arch/mips/kernel/idle.c
arch/mips/kernel/spram.c
arch/mips/kernel/traps.c
arch/mips/mm/c-r4k.c
arch/mips/mm/sc-mips.c
arch/mips/oprofile/common.c
arch/mips/oprofile/op_model_mipsxx.c