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(parent: 1dc001f) | patch
mmc: meson_gx_mmc: control ddr_mode bit
authorJaehoon Chung <jh80.chung@samsung.com>
Tue, 10 Nov 2020 07:44:53 +0000 (16:44 +0900)
committerMarek Szyprowski <m.szyprowski@samsung.com>
Mon, 15 Nov 2021 10:37:12 +0000 (11:37 +0100)
commit2654e9c2925cb92c381e980d15cbf267ef1886cd
treeb5cee20eb56ab063bce739a6996d5e6d860de6cetree | snapshot
parent1dc001fb2ef9d1daf40739d5d94a6723e1897b28commit | diff
mmc: meson_gx_mmc: control ddr_mode bit

EMMC_CFG register has a cfg_ddr bit(BIT[2]).
It needs to set when mmc is running to ddr mode.
Otherwise, its bit should be cleared.
CFG_DDR[2] - 1: DDR mode, 0: SDR mode

Change-Id: I5b1ddc6492e9c0d90e974fa31b13eacdee6e38e3
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
arch/arm/include/asm/arch-meson/sd_emmc.h diff | blob | history
drivers/mmc/meson_gx_mmc.c diff | blob | history
Domain: System / Kernel;