AMDGPU/GlobalISel: Round up image operations with 5, 6 or 7 addresses
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Sat, 8 Feb 2020 21:53:04 +0000 (16:53 -0500)
committerMatt Arsenault <arsenm2@gmail.com>
Mon, 30 Mar 2020 21:02:47 +0000 (17:02 -0400)
commit2641ba52a9c66d1d83e25646228a2574f3c22773
treede2e1b6495a25729f4ea2f407b22f9c00e148f70
parent42d5609809836aceff41f78ab652a882d4982260
AMDGPU/GlobalISel: Round up image operations with 5, 6 or 7 addresses

The instruction definitions are missing for these register types, so
round up to 8 like the DAG.
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll