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(parent: e735b98) | patch
tlb: mmu_gather: add tlb_flush_*_range APIs
authorPeter Zijlstra (Intel) <peterz@infradead.org>
Thu, 25 Jun 2020 08:03:12 +0000 (16:03 +0800)
committerCatalin Marinas <catalin.marinas@arm.com>
Tue, 7 Jul 2020 10:23:46 +0000 (11:23 +0100)
commit2631ed00b0498810f8d5c2163c6b5270d893687b
tree6480bf9dcda9ef3f0f7695ea025804b91049c990tree | snapshot
parente735b98a5fe08c0f50f9fdc3e3a844e3638e6649commit | diff
tlb: mmu_gather: add tlb_flush_*_range APIs

tlb_flush_{pte|pmd|pud|p4d}_range() adjust the tlb->start and
tlb->end, then set corresponding cleared_*.

Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20200625080314.230-5-yezhenyu2@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
include/asm-generic/tlb.h diff | blob | history
Domain: System / Kernel;