[RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32.
authorCraig Topper <craig.topper@sifive.com>
Mon, 26 Apr 2021 22:29:34 +0000 (15:29 -0700)
committerCraig Topper <craig.topper@sifive.com>
Mon, 26 Apr 2021 22:43:02 +0000 (15:43 -0700)
commit262a72f50f1887591558ce0f521a5f7d3a17e2c2
tree417f484372d53f9ef7113ff18325bda26fcd083b
parent254e289d45337ec1da930ef93b4b1dd92f791153
[RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32.

Reduces the amount of vector ALU operations and reduces vector
register pressure.
24 files changed:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll
llvm/test/CodeGen/RISCV/rvv/vsra-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll
llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll